1. Field of Invention
The present invention relates to the transmission of digital data signals on electrical busses and more particularly to an improved duplicated circuit arrangement wherein the number of simultaneous switches in the redundant devices is significantly reduced. In addition, according to the invention, it is possible to select only the operative sections of said devices to continue processing.
2. Description of the Prior Art
On the one hand, circuit duplication is a method often used to detect failures in systems where a high confidence level in failure detection is required. In accordance with such a method, two identical processing elements perform the same operations on the same data, their results are continuously compared, and a failure is detected if they do not match.
On the other hand, it is also well known that the data transmission rate between chips or modules on electrical busses is restricted by certain limitations related to the maximum number of simultaneously switching output drivers allowed. These limitations are due to voltage or current noise induced into the voltage distribution and signal lines when output drivers are simultaneously driving a large number of data bus lines. Known solutions are accompanied by heavy penalties in terms of packaging development and cost: complex voltage distribution, complicated line drivers and receivers, reduced bus width, as well as in terms of machine speed because it results in slower signal transmission due to the necessity of using controlled delayed transients in order to avoid the said phenomena of simultaneous switching.
FIG. 1 illustrates a known circuit arrangement of the prior art referenced 1 in the drawing, which embodies duplicated hardware. It will be used to set forth the problems raised by the simultaneous switching of output drivers when a duplicated circuit is implemented in a system. It is assumed that devices 2 and 3 are identical and therefore perform the same operation (when not defective) under the control of the main processor 4. Devices 2 and 3 may be for example, the floating point co-processor chip described in an article entitled:"Custom floating point chip designed with a cohesive structured method" by B. Desrosiers et al, published in the proceedings of the IEEE International Conference on Computer Design: VLSI in Computers ICCD'86 pp 402-405. The person skilled in the art will find in this article all the technical background to implement the present invention, such as clock distribution, sequencing, etc. In FIG. 1, device 2 is considered the master and device 3, the slave. Each device (2;3) is comprised of a processing element (5;6), working on a P bit word, for example, thirty six bits or four bytes, a send/receive circuit (7;8) and a compare circuit (9;10) respectively. An example of an appropriate processing element is shown in FIG. 1 of the above mentioned article.
Send/receive circuits 7 and 8 assure transmission of the four bytes (thirty two bits of data plus four parity bits) to and from the main data bus 11 of main processor 4, through bidirectional busses 12 and 13 respectively. Busses 12 and 13 are referenced to the device data bus, to be distinguished from the main processor data bus, referenced to the main data bus. However, it is to be noted that send/receive circuit 8 functionally operates only as a receiver in normal operation. Send/receive circuits 7 and 8 also assure bidirectional transmission of the P bit word to and from processing elements 5 and 6 on, busses 14 and 15 respectively.
Send/receive circuits 7 and 8 are comprised of a plurality of basic units, one per bit. Each unit is constituted of a separate output driver and receiver, having the output of the driver and the input of the receiver forming a common node connected to a line of the bus. Standard three state drivers and receivers are used for that application. An on-chip tristate driver is depicted in an article of the IBM Technical Disclosure Bulletin Vol. 25, No. 5, Oct. 1982, pages 2347-2348. The high impedance state of the drivers forming parts of send/receive circuits 7 and 8 is under the control of main processor 4 through control (inhibit) lines SR1 and SR2.
Compare circuit 9, which compares the bytes available on bus 14A after processing in processing element 5 with the bytes available on bus 14B, received from bus 12, is of no real utility in normal operation in the sense that it is not used to compare the validity of data after processing in the two processing elements, but it is of some interest since it may check the integrity of the send/receive circuit (drivers and receivers). Bus 14A is a unidirectional bus which connects the outputs of processing element 5 to the inputs of the drivers of send/receive circuits 7. Bus 14B is a unidirectional bus which connects the inputs of processing element 5 to the outputs of receivers of send/receive circuit 7. Busses 14A and 14B form the internal bus 14 of device 2. Compare circuit 10 compares the bytes processed by processing element 6 available on bus 15A with bytes received from device 2 and available on bus 15B. Bus 15A is a unidirectional bus which connects the outputs of processing element 6 to the inputs of drivers of send/receive circuit 8. Bus 15B is a unidirectional bus which connects the inputs of processing element 6 to the outputs of the receivers of send/receive circuit 8. Busses 16A and 15B form the internal bus 15 of device 3. The output of compare circuit 10 at node 16 provides the check out (CHKOUT) bit on line 17 for the main processor 4.
When all the drivers are not inhibited, the corresponding send/receive circuit is said to be in the SEND mode, and so is the corresponding device.
When all the drivers are inhibited, they are in the high impedance state, the corresponding send/receive circuit is said to be in the RECEIVE mode, and so is the corresponding device.
The operation takes place in three steps:
(a) Main processor 4 sets send/receive circuits 7 and 8 of devices 2 and 3 respectively to the RECEIVE mode through lines SR1 and SR2, and sends them data through busses 11, 12 and 13.
(b) Both processing elements 5 and 6 of devices 2 and 3 respectively process the data.
(c) Main processor 4 sets send/receive circuit 7 of device 2 to the SEND mode and send/receive circuit 8 of device 3 to the RECEIVE mode. When settled in the RECEIVE mode during this step, the send/receive circuit will also allow the compare function. This operating mode of the send/receive circuit will be referenced as the RECEIVE/COMPARE mode. This particular step is called the TRANSMISSION step. Send/receive circuit 7 of device 2 transmits the processed data to the main processor 4 and to device 3 through busses 11 and 12. Compare circuit 10 of device 3 compares its own internal results available on bus 15A with the data received from device 2 available on bus 15B and sends the comparison result to the main processor via output node 16 and line 17. The output of compare circuit 9 is available at node 18 and line 19, but has the limited use mentioned in the above operation.
Therefore, in normal operation, device 3 (the slave) is used only for checking purposes while device 2 (the master) assures the data exchange with the main processor 4.
However, in case of mismatch the main processor stops the task in progress and starts a diagnostic routine to determine which one of the two devices (in fact which processing element) is the failing one. The good device is then switched to operate as the master while the failing one is disabled (output drivers forced into the high impedance state). Processing can then continue in a degraded operation without the previous checking capability until repair.
There is no means of selecting the operative sections of the processing elements of any devices while maintaining some checking capability.
The duplicated circuit arrangement of two redundant devices shown in FIG. 1, has still another, but primary, disadvantage: device 2 may be an integrated semiconductor chip or an electronic module and during the TRANSMISSION step where bits are transmitted on data bus 12, it may happen that a majority, if not all the P (e.g. thirty six) drivers forming the emitting portion of the send/receive circuit 7, may switch simultaneously, therefore producing the above-mentioned undesirable noise effects.
To date, the only known way of reducing that phenomenon of simultaneous switching is to properly use controlled delayed transients at the cost of an important reduction of the data transmission speed.
A 4 byte wide bidirectional data bus 11 has been chosen to illustrate this invention but any other configuration can be used: unidirectional busses or busses of different width.
As new semiconductor technologies arise, there is a continuous effort in developing circuits and applications involving both redundant devices, wide data busses (such as handling 64 or 128 bits) and operating at very high frequency. As a result, there is still an obvious need for an improved circuit arrangement of two redundant devices alleviating all the problems related to the simultaneous switching of output drivers mentioned above.